With progress in miniaturization and the increase in operating speed of electronic information equipment, rapid progress has been achieved in reducing the size and increasing the number of pins of semiconductor IC packages. From the viewpoint of high-density assembly, it is believed that the so-called bare chip assembly, an assembly method that omits the package, might prove to be the optimal assembly method. However, due to problems related to reliability and assembly, this method has not yet been widely adopted in general home appliances. In particular, extensive studies and development are being carried out on the CSP (Chip Size Package). CSP is a type of high-density package in which the density is increased so that the size of the IC package becomes similar to or only slightly larger than the chip size.
FIG. 11 is a diagram illustrating an example of the conventional CSP type package. On flexible insulating substrate (2) on which copper pattern (3) has been formed, semiconductor IC chip (4) is carried on flexible insulating substrate (2). Said flexible insulating substrate (2) may be made of condensed type (nonthermoplastic) polyimide resin, such as films of Upilex [transliteration] (trade names) and Kapton (trade name). In order to realize insulation between chip (4) and conductor pattern (3), epoxy-based solder resist (26) is applied to the surface of insulating base material (2), so as to form substrate A. By means of insulating epoxy-based die-attaching material (27), chip (4) is bonded on substrate D. After wire bonding, the chip is molded, and solder balls (5) are moved to the lower surface of substrate D, forming CSP type package.
However, the aforementioned package with the conventional structure has the following disadvantages:
(1) The glass transition temperature Tg of the epoxy base die-attaching material for fixing the chip is in the range of about -10 to 150.degree. C. In the case of high-temperature reflow at temperature higher than 200.degree. C. for forming the solder bumps, the bonding strength decreases. As a result, it becomes impossible to maintain the bonding between the substrate and chip during reflow, and cracks form on the package. PA1 (2) The adhesion between the molding material for sealing the chip and the epoxy-based solder resist coated on the substrate is relatively low (with a shear strength in the range of about 70-200 kg/mm2), and in the case of reflow, separation takes place between the molding material and the solder resist on the periphery of the package. PA1 (3) In the manufacturing operation of the package, two methods may be adopted to form the conductor pattern on the flexible insulating base material. In one of these methods, after the epoxy-based adhesive is coated on the surface of the insulating base material (adhesive layer (28) in FIG. 11), a copper foil is laminated and it is then etched to form the conductor pattern. In the other method, after a copper film pattern is formed on the insulating base material by sputtering or electrolytic plating, the conductor pattern is formed by means of electrolytic plating. However, for the former, after the copper foil is laminated, curing must be performed at about 170.degree. C. for about 1 h. In this case, the gs from the adhesive may contaminate the copper foil. The cleaning operation of the copper foil by means of plasma cleaning leads to an increase in the number of manufacturing steps of the package, and the cost of the package is increased. In the latter case, for formation of the copper film pattern by means of sputtering or electrolytic plating, the productivity is poor, and the cost of the package is increased. PA1 (4) In the high-density assembly operation, a laminated substrate having multiple layers of the conductor pattern in the thickness direction of the substrate is highly demanded. For the conventional condensed type polyimide substrate, an adhesive is needed to bond the various layers of insulating base material to each other. This, however, increases the number of the manufacturing steps of the laminated substrate and increases the cost. PA1 (5) When the chip is assembled, in some cases, the amount of the epoxy-based die-attaching material for fixing the chip to the substrate may be insufficient to cover the entire lower surface of the chip. In such cases, the molding material enters the gap between the chip and the substrate in the resin molding operation; due to the difference between the die-attaching material and the molding material with respect to the linear expansion coefficient and the tensile modulus, separation of the interface between the die-attaching material and the molding material takes place. In the case of a rapid change in temperature, due to the aforementioned separation, the copper pattern becomes stressed, and the copper pattern may be broken. On the other hand, when the amount of the die-attaching material is too large, the die-attaching material flows to and covers the region of the conductor pattern where wire bonding is needed. Consequently, in assembly of the chip, it is necessary to control the amount of the aforementioned die-attaching material precisely. PA1 (6) Due to the difference in the linear expansion coefficients between the insulating base material made of condensation type polyimide resin and the epoxy-based solder resist coated on the insulating base material, warping occurs, leading to a decrease in the productivity of the package.
The purpose of the present invention is to enable assembly of the aforementioned semiconductor IC chip on a substrate without using the aforementioned epoxy-based die-attaching material, so that the aforementioned problems which accompany the use of epoxy-based die-attaching material can be avoided.
Another purpose of the present invention is to get rid of the aforementioned solder resist so as to realize insulation between the chip and the substrate, and to solve the aforementioned problems that used to take place between the solder resist and substrate or molding material.
Yet another purpose of the present invention is to provide a method in which a conductor pattern can be formed on the substrate for assembly of chip in a process with fewer steps and at a lower cost.
Yet another purpose of the present invention is to realize a laminated substrate used in the semiconductor device without using the conventional adhesive.